本文提出以收縮陣列(Systolic Array)設計聚類分析，所提出之架構具有規律性與模組化之特性，且同樣的架構有亦可以應用在輸入資料數目改變之情況。另外在VLSI架構中之處理元素(processing elements)間採用本地通訊(local communication)，故適合VLSI之製造。利用本文所提出之新架構，高速度之聚類分析可用電路複雜度較低之VLSI來實現。
This paper presents a VLSI architecture for the squared error clustering analysis. The proposed VLSI architecture exploits 2-dimensional systolic array which uses high degree of parallel and pipelined processing. The architecture dramatically reduces the immense number of processing elements (PEs) which are required by previous architectures. Furthermore, the proposed architecture requires only local communication between adjacent PEs. Moreover, the same architecture can be utilized for applications with a variable number of input patterns. Also, unlike previous architectures, the patterns are applied to the inputs in pattern serial format which can save a large number of pin counts, and therefore the proposed architecture is attractive for VLSI implementation.
