Design of UART with RTL Based BIST

CCUR > College of Natural Science and Engineering > College of Engineering > College of Engineering > Chinese Culture University Hwa Kang Journal of Engineering > Item 987654321/22219

Please use this identifier to cite or link to this item: https://irlib.pccu.edu.tw/handle/987654321/22219

Title:	Design of UART with RTL Based BIST
Authors:	林嘉洤朱奉昇張育榮
Contributors:	工學院
Keywords:	非同步接收傳送器內建自我測試線性回饋移位暫存器 UART BIST LFSR
Date:	2003-06-01
Issue Date:	2012-05-09 14:32:26 (UTC+8)
Abstract:	本文提出－具備內建自我測試的通用非同步接收傳送器之設計方式。以VHDL硬體描述語言作爲實現該系統的工具。內建自我測試的部分選擇以線性回饋移位暫存器(Linear Feedback Shift Register, LFSR)所產生的假亂數測試序列作爲待測電路的測試流。以ModelSim軟體模擬所撰寫的VHDL程式在功能上的正確性與評估其錯誤覆蓋率。分析結果顯示，此一系統總共耗用1673個邏輯閘，而全域錯誤涵蓋能力則達到95.69%。 A commercial universal asynchronous receiver transmitter (UART) with a built-in self test (BIST) circuit is proposed. In this paper; VHDL is selected for realizing the RTL based UART and BIST system. A pseudorandom test pattern generator, linear feedback shift register (LFSR), is chosen to produce the testing stream. The proposed VHDL programs are simulated by ModelSim and the code coverage is also considered. In addition, the synthesis tools are used for verifying its synthesizability. The analysis results show that 1673 gates are totally used in the implementation of this design, and the capability of global code coverage has up to 95.69%.
Relation:	華岡工程學報 17期 p.147 -160
Appears in Collections:	[工學院] 學報-華岡工程學報

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