本文主要在介紹，如何藉由對於指令參考行爲的瞭解，來選擇最佳指令快取記憶體的結構，而使其獲得最佳表現。首先介紹程式負載的分類，使快取記憶體設計者能藉此分類，在做快取記憶體表現評估時，僅利用對少許程式負載的分析，即可得到完整的結果。再者介紹，快取記憶體結構中，行區大小的選擇，乃根據動態基本區段的大小以及行區的使用率來決定。聯結度的選擇，乃根據衝突錯失及硬體價目的大小而定。而快取記憶體的尺寸，則取決於有效工作空間和前置空間的大小。最後再介紹，編譯器及程式的寫作者，如何利用相位分離的特性來降低錯失率。
This paper presents the considerations of choosing an optimal instruction cache configuration including the line size, the associativity, and the cache size by examining the instruction references behavior. A program taxonomy classifies instruction reference streams into three class of workloads. This helps a cache designer both in deciding the best configuration and in evaluating all spectrum of workloads with a minimal test set. The line size is determined by the size of dynamic basic blocks and the line utilization of a trace. The associativity depends on the hit time and the hardware cost. The optimal cache size is obtained by examining the effective working space and the header of a trace. Finally, the phase separation concept is introduced. Programers and compiler writer can take advantage of the characteristics to reduce the miss ratio without other expenses.
