A thermally robust Ni-FUSI process using in 65 nm CMOS technology

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Title:	A thermally robust Ni-FUSI process using in 65 nm CMOS technology
Authors:	Tan, S. Y.;Sung, C. L.;Wu, W. F.
Contributors:	電機系
Date:	2007
Issue Date:	2009-11-13 14:15:38 (UTC+8)
Abstract:	The interest in the low resistivity fully silicided (FUSI) gate increased significantly because of promising in use as contact to the source, drain, and gate for sub-65 nm/45 nm CMOS devices. NiSi is potentially an attractive material due to its capability to maintain low resistivity even for channel length down to 100 run. The Formation of thermally stable silicide gates is important for improving the devices fabrication processes. In order to obtain a thermally stable Ni-FUSI gate electrode, we introduced a two-step annealing process associated with properly tuned thickness of the initial Ni film and additional of implantation of BF2 during the poly-gate formation to push the transformation of NiSi2 to higher temperatures at about 900 degrees C and retard agglomeration. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. For the first time, we established an effective way to identify the phase transformations by some nondestructive techniques such as X-ray diffraction, sheet resistance measurement and AFM analysis. The correlations between its electrical and morphological changes during Ni-Si phase transformation were presented. Furthermore, the effect with addition amount of BF2 impurities into NiSi was investigated. F-incorporation demonstrated some improvements in both morphology and phase stability of the NiSi films at high processing temperatures.
Relation:	JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS Volume: 18 Issue: 8 Pages: 847-854
Appears in Collections:	[Department of Electrical Engineering ] journal articles

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