當二氧化矽當作閘極氧化層的製程方式，縮小到2nm以下時，會造成兩個主要問題，一是漏電流與短通道效應等問題隨之而生，而高介電常數材料能有效的抑制漏電流，並且在相同的等效氧化層厚度下增加實際介電層的厚度。二則是高的閘極片電阻值會造成元件的傳遞延遲，所以使用金屬閘極(Metal Gate)來取代多晶矽閘極，因金屬閘極可解決閘極空乏效應、硼離子穿透(Boron Penetration)、降低閘極片電阻及提高在高介電質材料(High-k Materials)上的相容性等問題。本文主要探討金屬閘極TiN堆疊不同厚度下，利用MIS(Metal-insulator-semiconductor)電容結構沉積HfSiO薄膜，並觀察量測其元件的電容電壓(C-V)值及漏電流密度對電壓(J-V)值，來比較其各個不同條件的差異性。
When the silicon dioxide as gate oxide process narrows below 2 nm, it will cause two main problems, first, the leakage current and short channel effect will occur. In addition, the highly dielectric constant material can effectively suppress leakage current, and at the same
equivalent oxide thickness increase the actual thickness of the dielectric layer. Secondly,the delay of devices transmission will cause a highly gate sheet resistance, it used to replace poly-si gate by metal gate, because metal gate can solve the depletion effect, Boron
Penetration, decrease gate sheet resistance and improve the compatibility of high-k materials.This article explores TiN metal gate in different thickness, exploiting MIS (Metal-insulator-semiconductor) capacitors deposited HfSiO thin films. We also observed and measured the value of the capacitance voltage (C-V) and leakage current density versus
voltage (J-V) to compare the difference between the different conditions.
